//**************************************************
// Description: async fifo between ETH system and NP system
//**************************************************

module assemble_async_fifo (
    input                   portA_clk , // ETH clk(100MHz)
    input                   portB_clk , // NP clk(312.5MHz)
    input                   rst ,
    input   [11:0]          ram_dp_cfg_register,
    // write FIFO port A
    input                   ACTION_wr_en ,
    input   [29:0]          ACTION_wr_order ,
    input   [33:0]          ACTION_wr_addr ,
    input   [31:0]          ACTION_wr_data ,
    output                  rx_wr_full ,
    // write FIFO port B
    input                   rx_rd_en ,
    output  [29:0]          rx_rd_order ,
    output  [33:0]          rx_rd_addr ,
    output  [31:0]          rx_rd_data ,
    output                  rx_rd_empty ,

    // read FIFO port A
    input                   ACTION_rd_en ,
    output  [29:0]          ACTION_rd_order ,
    output  [33:0]          ACTION_rd_addr ,
    output  [31:0]          ACTION_rd_data ,
    output                  ACTION_rd_empty ,
    // read FIFO port B
    input                   tx_wr_en ,
    input   [29:0]          tx_wr_order ,
    input   [33:0]          tx_wr_addr ,
    input   [31:0]          tx_wr_data ,
    output                  tx_wr_full
) ;
`ifdef FPGA_MODE
    write_asyncFIFO_order_addr_data_256d_96w inst_rx_async_fifo(
        .rst    (rst),        // input wire rst
        .wr_clk (portA_clk),  // input wire wr_clk
        .rd_clk (portB_clk),  // input wire rd_clk

        .wr_en  (ACTION_wr_en),    // input wire wr_en
        .din    ({ACTION_wr_order , ACTION_wr_addr , ACTION_wr_data}),  // input wire [95 : 0] din
        .full   (rx_wr_full),      // output wire full

        .rd_en  (rx_rd_en),    // input wire rd_en
        .dout   ({rx_rd_order , rx_rd_addr , rx_rd_data}),              // output wire [95 : 0] dout
        .empty  (rx_rd_empty)    // output wire empty
    ) ;

    read_asyncFIFO_order_addr_data_256d_96w inst_tx_async_fifo(
        .rst    (rst),        // input wire rst
        .wr_clk (portB_clk),  // input wire wr_clk
        .rd_clk (portA_clk),  // input wire rd_clk

        .wr_en  (tx_wr_en),    // input wire wr_en
        .din    ({tx_wr_order , tx_wr_addr , tx_wr_data}),  // input wire [95 : 0] din
        .full   (tx_wr_full),      // output wire full

        .rd_en  (ACTION_rd_en),    // input wire rd_en
        .dout   ({ACTION_rd_order , ACTION_rd_addr , ACTION_rd_data}),              // output wire [95 : 0] dout
        .empty  (ACTION_rd_empty)    // output wire empty
    ) ;
`else
    asyncfifo_256d_96w_wrapper inst_rx_async_fifo(
        .rst    (rst),        // input wire rst
        .wr_clk (portA_clk),  // input wire wr_clk
        .rd_clk (portB_clk),  // input wire rd_clk
        .ram_dp_cfg_register(ram_dp_cfg_register),

        .wr_en  (ACTION_wr_en),    // input wire wr_en
        .din    ({ACTION_wr_order , ACTION_wr_addr , ACTION_wr_data}),  // input wire [95 : 0] din
        .full   (rx_wr_full),      // output wire full

        .rd_en  (rx_rd_en),    // input wire rd_en
        .dout   ({rx_rd_order , rx_rd_addr , rx_rd_data}),              // output wire [95 : 0] dout
        .empty  (rx_rd_empty)    // output wire empty
    ) ;

    asyncfifo_256d_96w_wrapper inst_tx_async_fifo(
        .rst    (rst),        // input wire rst
        .wr_clk (portB_clk),  // input wire wr_clk
        .rd_clk (portA_clk),  // input wire rd_clk
        .ram_dp_cfg_register(ram_dp_cfg_register),

        .wr_en  (tx_wr_en),    // input wire wr_en
        .din    ({tx_wr_order , tx_wr_addr , tx_wr_data}),  // input wire [95 : 0] din
        .full   (tx_wr_full),      // output wire full

        .rd_en  (ACTION_rd_en),    // input wire rd_en
        .dout   ({ACTION_rd_order , ACTION_rd_addr , ACTION_rd_data}),              // output wire [95 : 0] dout
        .empty  (ACTION_rd_empty)    // output wire empty
    ) ;
`endif

endmodule